Set up the hardware, the contest system is not an easy task. At least, for system while taking the place of and must hold more and more logic gate, memory of allowing ASIC and ASSP SoC designer to debug and their extremely complicated apparatus of DSP lump, before giving and casting the factory to see them off for production. The contest system must be apt to programme, reliable with bearing.

SoCs of today is very complicated silicon. They include one or more processors that will carry out the software. The software code that they run is totally a part of the last system as important as silicon. Software and silicon must be as having no solution sewing; If there is a question, it may be the software, or it may be silicon.

The designer can only do so much software test about a development host computer. There is not reasonable host’s development system that can reflect the true dual character of the goal SoC. You can really move ahead simultaneously only in the abundant test of original place alikely, dispute such a question with resources intactly in data, can’t appraise the question with that late too. Simulation is not a feasible solution; It is only too slow can’t allow the implementation of any real code.

So engineer use contest system suitable for, cross 20 easy to verify those semiconductor advanced ICs most that industry can build year. The seller of custom ICs person who offers motive force contest for great majority, these contest systems taken the place of designs oneself. Then they will pass their users expenses of custom IC development, will make the ability of more contests struggle with more urgent IC development budget and forbid the expenses for the company.

In 2001, Eve gave up the tradition through the system based on that its contest is on Xilinx FPGAs. The goal is the confirmation expenses of ownership in industry of offering the minimum hardware to help, like the implementation pace through being high, large capacity (show up to 1 billion doors today) Combination realize like that, design quickly because it revise, flexible and ability of debugging strong, each dollar and each of minimum expenses of door and most cycles. In addition, we should want the system easy to use suitable for ASIC designer that may not be familiar with FPGA is designed.

As a result ZeBu ‘ ” A defect ” ) Contest system. Our persons who have already developed 6 generations of contests now, it is ZeBu server among them most recently.

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